7. Registers

7.1 Parallel Data Register

A set of N data flip flops connected as shown in the above diagram constitutes a parallel data or buffer register of length N. It is used to capture and store an N-bit word X={x_i,i=1,N} Both the bits of the word and the load signal must precede the clock edge by the set-up time and remain constant for a further hold time following the edge. If load is high following the edge q_i=x_i. The register contents are up-dated following each clock pulse. When the load command signal is low, then the contents are simply circulated. New contents are only entered following a clock edge which occurs during a load=high state. The circulation technique is a simple and common method of avoiding unwanted updating on every clock edge. The d input of the i^th stage satisfies

In some cases the q_i are connected to tristate drivers. The entire register,including the drivers is then represented as shown and controlled by both load (write into) and enable (read out) signals. In the figure Q={q_i,i=1,N}. If no enable signal is indicated output is immediate, ie the output lines are always active.

7.2 Shift Registers

A portion of a shift register which shifts to the right is shown above. The equation for the data input of the i^th stage when shr=1 is

When shr=0, the contents are circulated. In the former case after each clock pulse the content of each inner flip flop is the previous content of the flip flop to the left. For a register of length N the output is x_out=q_N. Consider the case of N=3 and assume that the register is initially in the clear state with all q=0.

Consider the series of events in the following table.

The column labelled x_in represents the level on d₁ established before each indicated clock pulse. The states of the three flip flops are assumed after each indicated clock pulse. After the first clock pulse q₁ goes high in keeping with the corresponding data input. The data input for the second flip flop is the value of q₁ before the first clock pulse, which is 0. After the second clock pulse the previous value of the first flip flop is 1 so q₂ goes high. As can be seen the data at the input propagates through the register at each clock pulse. The output is a replica of the input delayed by 3 clock pulses. Shift registers are often used to delay information.

The shift register is also used for serial to parallel conversion and the inverse. N bits of serial information may be clocked in from x_in after N clock pulses. If each q_i is connected to a line through a tristate driver, the N bit word can be read out in parallel with an enable command.

The above circuit illustrates a register which can be loaded serially as a shift right shift register or may be loaded in parallel as a buffer register. The equations for the data inputs are

Tri state drivers are explicitly indicated for the two MSB. Data input either serially or in parallel can then be read out in parallel with an enable signal. It can also be read out serially with shr high from the LSB. Also indicated is a common register feature, a clear line which asynchronously sets all q_i=0 when high.

For the shift left function the data inputs satisfy

These may be combined with an shl signal as in Eqn(7.3). Using three command signals, load, shr, and shl, as well as four AND gates feeding a 3-input OR gate at each flip flop, it is possible to construct a register which shifts in either direction and acts as a parallel device upon command.

7.4 Asynchronous Counter

Counting events such as the passage of vehicles at a point on a road, or the number of items automatically dispensed to a container is a common activity. This task may be accomplished using a register consisting of toggle flip flops.

In the circuit shown above the J-K flip flops are set into the toggle mode when count is high, and the hold mode when count is low. Note that FF2 and FF3 clock inputs are connected to the complementary outputs of the respective preceding flip flop. The transition is then coincident with the falling edge of the direct outputs shown in the diagram. The circuit is drawn following the normal convention of signal flow from left to right. Note that this results in a reversal of the bit order to form the required word, as indicated by the connection of the FF1 to the LSB line and FFN to the MSB where N=3 in this example. Formally the register contents form a word Y={y_i,i=1,N} where y_i=q_N+1-i. The register is assumed to be initially cleared. The clear line is not shown. From the timing diagram below the circuit, which it must be emphasized does not include the effects of propagation delay, the following table for y may be constructed.

The contents of the register are the standard binary code (in reverse order) for the number of input pulses. While the input in the diagram was represented as a square wave typical of a system clock this is not at all necessary. In many applications the input is normally in the form of pulses which are randomly spaced. The situation shown in the diagram would arise in a frequency meter. In such a device the sinusoidal input is converted to a square wave and the count line is held high for one second. The device then returns to the hold mode and the contents, corresponding to the number of cycles per second is displayed. Obviously the maximum number of input pulses that can be counted correctly in an N-bit register is 2^N-1.

Notice that the arrangement violates the synchronous condition since the clock inputs are not directly connected to a common source. The transition at each flip flop is one propagation delay later than that of the preceding one. For an N-bit counter the contents are not settled until N propagation delays following the input. The asynchronous counter is often called a ripple counter, since the delay ripples through from input to output. The minimum spacing between inputs must be equal to the sum of N propagation delays and the required read time for correct counting.

This device may also be used as a frequency divider, in which case q₃ in the above example acts as an output. The output frequency is 1/8 of the input frequency. Since in this application, it is not necessary to ascertain the register contents, the ripple is not a limitation.

The first two stages of an asynchronous up/down counter are shown in the adjacent diagram. The interior interconnections are comprised of a two input multiplexer controlled by the down logical signal. When down is set high the successive clock inputs are connected to the direct outputs of the preceding flip flops, rather than the complements as for the counter described previously. For such a situation the contents decrement on each clock pulse, assuming count is high. Thus the first input following a clear sets q_i=1,i=1,N. With down set low the device operates as an up counter.

The above arrangement illustrates conceptually the use of a buffer register and an up counter as a digital timer. For simplicity assume the clock frequency is 1 Hz. The preset time is then the word representing the binary coded integer for the number of seconds. This may be derived by a keyboard and a decimal to binary converter. This word is loaded asynchronously into an unclocked buffer register, the output of which is connected to one input word of a digital comparator. An important aspect of registers is the start up state, attained when power is first applied. A simple technique of defining the start up state is to generate it from the power on condition considered as a logical variable. In this case it is assumed the power on transition generates a clear signal so the initial counter content is zero. The circuitry is not shown. The logical variable start gates on the clock and sets the count line. Actually, the clock gate should be delayed sufficiently to ensure the count line has settled. The digital comparator output sets high when the input word from the counter matches that from the buffer register, clearing the counter and resetting the control flip flop in preparation for another cycle. The application assumes that the error caused by the ripple through propagation delay and clock gate delay is acceptable for the time scale of interest. The digital comparison is accomplished in two steps. First the complement of XOR for each pair of corresponding bits is determined. Then a grand AND of these forms the output. For two 3-bit words X and Y the output z can be written

With the gated clock replaced by a sensor output, the device becomes a preset count counter used, for example in dispensing a given number of items into a container.

7.5 Synchronous Counters

The lack of synchrony in the ripple counter makes the device unsuitable for applications in digital systems as, for example, a program counter. In a synchronous device all transitions must occur at the clock edge, so all flip flop clock inputs must be connected to a common signal. In this case alternate means must be devised so that the register will cycle through its states in the required order. This can be done in general by making the j and k inputs present before the clock edge have appropriate values so that the required transition to the new state occurs when the device is clocked. This can only be achieved by making the j and k variables functions of the existing register state, Q={q_i,i=1,N}. A useful simplification arises if the constraint j_i=k_i,i=1,N is introduced. This is obviously accomplished in practice by connecting the two in common. In this situation there are only two possible modes, toggle when j=k=1 and hold when j=k=0. In the first case the new flip flop state is the complement of the old. In the second, the new state is identical to the old. The required functions j_i(Q) can be determined by the standard methods of truth table analysis. The specific example of N=3 will be examined. The following table is the combined truth tables for all three j inputs, for a synchronous up counter. In analysing the table, recall that the value of j at any time is determined by the desired transition for that flip flop at the next clock pulse.

Consider the entries for the third clock pulse. For the current state 011 to become 100 at the next clock pulse, number 4, each of the three flip flops must toggle. Hence each must have j=1 when the register is in the 011 state. On the other hand for the transition 100 to 101 to be induced by the arrival of the fifth clock pulse ff1 and ff2 must hold their old value and only ff3 must toggle. Notice it is necessary to include the overflow transition 111 to 000 to obtain the complete truth table. The solutions for j₂ and j₃ may easily be obtained by inspection as j₂=q₃ and j₃=1. Also since j₁=1 only when both q₂ and q₃ are 1, j₁=q₂q₃.

A circuit comprising a 3 bit controlled synchronous up-counter is illustrated above. Below the circuit are the Karnaugh maps for the j inputs of the first two flip flops also giving the expressions determined by inspection of the truth table. An additional logical variable designated count has been put in AND with these functions so that with count=1 the conditions are met while for count=0 all flip flops are in the hold mode and the contents are frozen. Extension to longer registers follows the same pattern with

j_i=q_i+1q_i+2...q_N, j_N=1.

It is clear that the above procedure may be used to design a register which cycles through the register set or a subset in any sequence. Two examples will be considered here. The first is a 3 bit synchronous down counter. The desired cycle and required j-values are first tabulated as follows.

By inspection j₁=q₂q₃,j₂=q₃,j₃=1. In general the N-bit down counter equations for all but j_N are obtained from the corresponding up counter equations by replacing each q by its complement.

The second example is a mod 6 counter which may be defined as a 3-bit up counter with a maximum of 5 rather than 7. The table is presented below. Notice that since only a subset of R₃ is involved the truth table is incomplete. Since the states 110 and 111 are never reached in the cycle, the values assigned to the j inputs are arbitrary. A problem could arise if in powering up the register randomly is put into one of these states and the configuration is such that it would remain trapped in this subset rather than the desired one. The simplest solution is to use the power on signal to set the register in a state of the desired subset such as 000, by clearing.

The solutions for j₁ and j₂ obtained from the corresponding Karnaugh maps are illustrated in the figure below.

An alternative method more amenable to generalization is to ensure that all flip flops are put into the reset condition, j=0,k=1 by the terminating word Q. For a mod n+1 counter this word is the minterm, m_n which may be detected by an Nx1 decoder. For example in the mod 6 counter above termination occurs for m₅=q₁q₂q_3. The design requirement is then that if the contents are not m_n ie, the decoder output is low, the j and k values are those corresponding to a standard synchronous up counter, but are altered to the reset values when the decoder output is high. Moreover, for a controlled counter it is required that the hold condition j=0,k=0 arise except when a count signal is high.

These conditions can be met using the following arrangement.

7.6 Time State Generators

There are many situations in which a repetitive procedure comprising a cycle is composed of several steps or phases. For example a 4-cylinder internal combustion engine has a four phase cycle as each cylinder in turn is compressed and expanded upon ignition. An N-phase time state generator is a device which issues N pulses of width T/N, where T is the period of the cycle, on N separate outputs.

7.6.1 Ring Counters

The ring counter is the simplest form of time state generator. It consists of an end around carry shift register with the output from the N^th flip flop fed back to the input. The register is designed to cycle through the subset of words of unit weight. It is thus restricted to N states and hence can generate N phases. A 3 phase time state generator using a 3 bit ring counter is illustrated above. The power signal is a pulse initiated when power is turned on. It is connected asynchronously to the reset inputs of FF1 and FF2, clearing these two elements. It is also connected asynchronously to the set input of FF3 presetting this element, so that turning on the power forces the register into the state 001. At the edge of the first clock pulse the state 100 is formed, giving a high output at q₁ defining the first phase interval j₁. The subsequent two edges bring the register into states 010 and 001 respectively and the outputs from FF2 and FF3 define the second and third phases. This completes the cycle. The term ring counter is somewhat misleading in that the register contents represent a non-standard code for the number of clock pulses. The device, in common with synchronous counters cycles in a prescribed manner through a subset of R_N. A generic term for such a device is a state machine.

7.6.2 Switch-tail Ring Counter

An interesting variation of the ring counter is shown below. In this arrangement the complementary output of FF3 is fed back to the shift register input and the entire register is initially cleared.

The sequence of states is shown in the following table.

Phase	State	Code
j1	000	q1q3
j2	100	q1q2
j3	110	q2q3
j4	111	q1q3
j5	011	q1q2
j6	001	q2q3

In this case the subset of R₃ through which the device cycles has 6 members. These consist of F,U and the asymmetrical states of weights 1 and 2. In general an N-bit arrangement generates 2N time states. In order to generate a specific phase signal j_i it is necessary to detect the occurrence of the corresponding state by decoding. In general this could be done using 6 of the 8 outputs of a standard 3-input decoder. In the above is shown a minimal decoding scheme applicable in this case, as another example.

7.6.3 Counter-based Time State Generator

As the switch-tail counter arrangement makes clear, any state machine can be used as a time state generator since the phase signals can be generated with a decoder. In particular, the synchronous up-counter coupled to a decoder is an "off-the-shelf" arrangement. If left in standard form it cycles through all the register states so 2^N phases are produced. By resetting the counter on a specific state shorter cycles may be produced.